The fabrication of integrated circuits, e.g., microelectronic devices, includes the building of multilevel wiring interconnect regions within the devices. To fabricate such structures, one or more interconnections are formed between first and second level wiring lines. To form these interconnects, openings are formed in the dielectric layer using conventional lithograhic and etching processes. The openings are filled with a metal to form the interconnect. This metal is typically Cu or AlCu. To continue with the build, the above process continues with the deposition of additional interlevel dielectric (ILD) layers to accommodate further processing of the integrated circuit.
The dielectric layers usually consists of a layer of oxide such, for example, as silicon oxides. However, it has been found that Cu metal introduces many integration challenges in combination with the dielectric layers. For example, copper is known to be a fast diffuser through dielectrics, especially in silicon dioxide. This leads to integration difficulty for copper damascene structures. That is, the copper will out diffuse into the dielectric potentially destroying the device. Thus, if copper diffuses from the interconnect wiring into the underlying active electrical devices, then these devices can fail to operate.
In an attempt to solve this problem, a dielectric diffusion barrier is placed in the via or trench prior to the deposition of the copper conductor. The standard industry approach for copper interconnects is to use barrier metals such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and/or tungsten nitride (WN) to prevent copper diffusion from the wires. However, it has been found that even a thick layer of such materials or combinations of these materials cannot completely top the out diffusion of copper. This poses a challenging task to designers as technology scales.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.